Multiple port random access memories are generally configured to include a number of ports, each of which typically represents an independent input/output path for accessing data stored in a memory array. A multiple port RAM may, for example, include a number of read ports and write ports, as well as a scan port for supporting scan-based testing of the memory device. It is noted that the number of read ports need not be the same as the number of write ports.
A significant problem encountered when attempting to increase the number of write ports for providing write access to a programmable memory array concerns the node capacitance at the input of the memory cells. In general, the capacitance at the input of a given memory cell increases with each additional write port connected thereto. Such increases in input node capacitance of the memory cell generally results in an appreciable degradation in memory cell write speed.
Another significant problem that arises when attempting to increase the number of write ports to a programmable memory array concerns a heightened potential of compromising data integrity or data stability within the memory cell that may occur during a charge sharing event. A write port for a conventional multiple write port RAM, for example, typically includes a pair of series connected transfer gates. Under certain conditions, a charge sharing event may occur in which the cumulative capacitance at the memory cell input and at a node defined between the two transfer gates may contribute to an inadvertent and potentially catastrophic flipping of the memory cell state.
Various conventional write port designs have heretofore failed to adequately address the undesirable increase in memory cell input capacitance and concomitant reduction in memory write speeds in multiple write port programmable memory devices. There is, therefore, a need for improved write port circuitry for multiple write port RAM applications which provides for reduced circuit capacitance and memory cell input capacitance, good performance and noise characteristics, and one that does not result in an increase in circuit element size or number of transistors. The present invention fulfills these and other needs.